1. Field of the Invention
The invention relates to a shift register and more particularly to a shift register without a feedback signal from an output signal of a post-stage shift register.
2. Description of the Related Art
Liquid crystal displays (LCD) have become the major product of displays, and minimizing the size and the weight of the LCDs, to dispose the driving circuit on the substrate of the LCD has become a major technology focus. Take the TFT LCD for example, since the amorphous Si process is the main technology, the low electron mobility of amorphous Si limits the size of the element formed by the amorphous Si process, such as a thin film transistor (TFT). If the transistor formed by the amorphous Si process wants to receive a larger current, the width of the channel of the transistor increases, thus, the layout area increases.
FIG. 1 is a circuit diagram of a conventional amorphous Si shift register. To ensure that the output of the shift register rapidly charges and discharges, the charging transistor T4 and the discharging transistors T5 and T6 receive larger current, thus, the width of those transistors is about a thousand micro-meters, and thus occupy larger layout areas. Moreover, the conventional shift register utilizes an output signal of a post-stage shift register to pull down the output signal, and if the shift register is the last-stage shift register, the output signal thereof may not completely discharge, such as shown in the dotted frame 20 of the FIG. 2. FIG. 2 is a timing diagram of the amorphous Si shift register of the FIG. 1. In FIG. 2, curve 21, 23, 25 and 27 respectively represents the charging and the discharging of the (N−1)th stage shift register, Nth stage shift register, (N+1)th stage shift register, and (N+2)th stage shift register. In FIG. 2, the (N+2)th stage shift register is the last-stage shift register, thus, the output signal thereof does not completely discharge, as shown by dotted frame 20. Take the output signal of the (N−1)th stage shift register for example, the discharge time thereof is about 25 μs and when the output signal of the Nth stage shift register charges, the output signal of the (N−1)th stage shift register does not discharge completely, thus, an overlap occurs, and this causes the incorrect LCD output.
Therefore, an amorphous Si shift register circuit capable of reducing the layout area and reducing or eliminating overlapping is desirable.